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• W2488334392 abstract "Nowadays, IoT devices are ubiquitous in our daily life. 3GPP Long Term Evolution (LTE) protocol is the backbone supporting the IoT ecosystem. Moreover, IoT-friendly LTE requires LTE chip to be both high performance and energy efficient. In this paper, we propose to use high level synthesis to design LTE chips. We develop a framework to explore the design space of LTE kernels with respect to different performance and power trade-offs using a commercial HLS tool. We present quantitative performance and power analysis for LTE kernels. Through systematic design space exploration, we can achieve on average 20X performance speedup, or 7.6X energy saving compared to the baseline design." @default.
• W2488334392 created "2016-08-23" @default.
• W2488334392 creator A5002704866 @default.
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• W2488334392 date "2015-11-01" @default.
• W2488334392 modified "2023-09-26" @default.
• W2488334392 title "Quantitative performance and power analysis of LTE using high level synthesis" @default.
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• W2488334392 doi "https://doi.org/10.1109/asicon.2015.7517024" @default.
• W2488334392 hasPublicationYear "2015" @default.
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