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- W2488396790 abstract "In Chapter 9, we discuss some real-life examples of cases where FV techniques were applied incorrectly, sometimes resulting in false positives: cases where a “formally proven” design turned out to contain errors. The simplest cases result from misuse or misunderstanding of the System Verilog language, which should be addressed by strong linting and manual reviews. Another class of these problems is vacuity issues, where part of the problem space is ignored; prevent these using tool features, good cover points, review of reset conditions, and simulation of assumptions. A third cause is implicit or misunderstood assumptions, addressable by careful review of assumptions and tool options. Finally, some false positives have resulted from a confused division of labor: be sure to have solid global owners for each verification area. By paying attention to these lessons from real projects, the reader should be able to prevent these issues from recurring in their own designs." @default.
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- W2488396790 date "2015-01-01" @default.
- W2488396790 modified "2023-09-28" @default.
- W2488396790 title "Formal verification’s greatest bloopers" @default.
- W2488396790 cites W1583654333 @default.
- W2488396790 doi "https://doi.org/10.1016/b978-0-12-800727-3.00009-5" @default.
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