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- W2488804552 abstract "Intel Xeon Phi coprocessors present a large amount of available parallelism in a single device. Large core counts (> 50) and wide SIMD vector instructions present a lot of available computation lanes of parallelism. Multithreaded applications became much more common when multicore processors became ubiquitous. Thread level parallelism has been made very easy with threading APIs such as OpenMP, CILK Plus, and Threading Building Blocks. In many cases, however, effective SIMD utilization is not as straightforward as multithreading. A purely scalar code can only use about 1/16th of the single precision FLOPs of a coprocessor, even while maintaining good work distribution among threads. Therefore, this chapter points out some characteristics about SIMD programming with Intel SPMD Program Compiler (ispc) in the context of evaluating fault tree expressions. Readers will see a typical progression of taking scalar code and mapping it effectively into ispc to get good vectorized code, to fully take advantage of the coprocessor’s compute performance." @default.
- W2488804552 created "2016-08-23" @default.
- W2488804552 creator A5013218669 @default.
- W2488804552 date "2015-01-01" @default.
- W2488804552 modified "2023-09-26" @default.
- W2488804552 title "Parallel Evaluation of Fault Tree Expressions" @default.
- W2488804552 doi "https://doi.org/10.1016/b978-0-12-802118-7.00006-6" @default.
- W2488804552 hasPublicationYear "2015" @default.
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