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• W2492384562 abstract "This chapter presents a summary of various fault-detection and fault-tolerance methods at various levels of a computing system: arithmetic circuit, field-programmable gate arrays (FPGA), program control flow, processor system, and algorithm. It also presents some of the works in these areas. Results show that the techniques discussed produce significant increases in system reliability. As computer chips become more complex and denser, with smaller devices, they and systems incorporating them become more and more vulnerable to faults arising from a myriad of sources like fabrication errors, operation extremes, and external disturbances. Computer systems are also being increasingly used in various economic- and life-critical environments. It is thus hoped that microprocessor and computer manufacturing undergoes a paradigm shift whereby reliability becomes an important metric, and fault tolerance capabilities of different degrees are explicitly designed in computer chips and systems to provide different levels of dependability and reliability needed in various application environments." @default.
• W2492384562 created "2016-08-23" @default.
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• W2492384562 date "2005-01-01" @default.
• W2492384562 modified "2023-09-27" @default.
• W2492384562 title "Fault Tolerance in Computer Systems—From Circuits to Algorithms**This work was supported in part by the U.S. Department of Defense under the MURI grant F49620-01-1-0436." @default.
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• W2492384562 doi "https://doi.org/10.1016/b978-012170960-0/50034-7" @default.
• W2492384562 hasPublicationYear "2005" @default.
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