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- W2495489345 abstract "Internal thermal problem has become a critical challenge in multi-core 3D ICs. The interlayer cooling system provided a new solution for this problem, and expanded the design space of multi-core microprocessor floorplan. This work proposes a thermal-aware floorplanner for multi-core 3D ICs with interlayer cooling, with iterative algorithm based on simulated annealing method. The results show that the maximal temperature is reduced by 15(^{circ }) C, and the temperature gradient is reduced by 28.4(^{circ }) C compared to the baseline design with 3 active device layers." @default.
- W2495489345 created "2016-08-23" @default.
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- W2495489345 date "2016-01-01" @default.
- W2495489345 modified "2023-09-24" @default.
- W2495489345 title "Thermal-Aware Floorplanner for Multi-core 3D ICs with Interlayer Cooling" @default.
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- W2495489345 doi "https://doi.org/10.1007/978-3-662-49283-3_3" @default.
- W2495489345 hasPublicationYear "2016" @default.
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