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- W2496005997 abstract "This paper presents a high performance hardware architecture of face recognition algorithm based on local binary pattern. Through the software implementation of the algorithm, the optimization of the data's widths and block size can be obtained. Then a hardware structure based on the algorithm is proposed. The histogram statistic and recognition can be handled concurrently with a ping-pang memory and the data throughput can be increased with the pipeline and parallel processing units. The proposed architecture is implemented in the Xilinx Virtext-7 FPGA VC707 evaluation board and is verified with a large number of training pictures. The design costs 5975 LUTs and the clock frequency can be up to 233MHz. For a library with one hundred thousand faces, the proposed design can recognize 1.7 faces per second and its recognition speed is 74 times faster than the software's in the general CPU platform." @default.
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- W2496005997 date "2015-11-01" @default.
- W2496005997 modified "2023-10-14" @default.
- W2496005997 title "Implementation of high performance hardware architecture of face recognition algorithm based on local binary pattern on FPGA" @default.
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- W2496005997 doi "https://doi.org/10.1109/asicon.2015.7516877" @default.
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