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• W2496353417 abstract "Monolithic three-dimensional integrated circuits (M3D ICs) are being advocated as the next generation of 3D integration beyond 3D ICs based on through-silicon-vias. Testing of the bottom layer of an M3D IC is necessary to target defects arising from the layered manufacturing process. We present an efficient design-for-test (DfT) method for the bottom layer by isolating it from the top layer. A bypass structure based on e-fuses is proposed to connect pairs of inter-layer vias (ILVs). In order to minimize the wire length between paired ILVs, an ILV-pairing problem is formulated and then solved using a technique based on maximum-weighted bipartite matching. The independent ILVs, i.e., those that are not paired, are made controllable and observable using four different types of DfT structures. A cost-optimization problem is solved to minimize the DfT cost. We present ILV-pairing and cost-optimization results for designs based on the ITC′02 benchmarks as well as for an industry design. We also present HSpice simulation results to show that testing using e-fuses is feasible." @default.
• W2496353417 created "2016-08-23" @default.
• W2496353417 creator A5021311475 @default.
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• W2496353417 date "2016-05-01" @default.
• W2496353417 modified "2023-09-25" @default.
• W2496353417 title "A design-for-test solution for monolithic 3D integrated circuits" @default.
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• W2496353417 doi "https://doi.org/10.1109/ets.2016.7519311" @default.
• W2496353417 hasPublicationYear "2016" @default.
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