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- W2499888942 abstract "In this paper, we present the design of a passive test chip with thermal test structures in the Metal 1 layer of the back-end of Line (BEOL) for the experimental thermal characterization of the inter-die thermal resistance of wafer-pairs fabricated by hybrid Cu/dielectric wafer-to-wafer bonding. The thermal test structures include heater elements and temperature sensors. The measurement data is combined with a modeling study to extract the thermal resistance of the bonded interface for the fabricated bonded wafer pair. The extracted thermal resistance of the die-die interface created by hybrid wafer-to-wafer bonding is compared to literature data on µbump stacking. The low thermal resistance of the thin bonded dielectric interface indicates that hybrid Cu/dielectric bonding is a promising technology to create 3D chip stacks with a low thermal die-to-die resistance." @default.
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- W2499888942 date "2016-05-01" @default.
- W2499888942 modified "2023-10-01" @default.
- W2499888942 title "Thermal characterization of the inter-die thermal resistance of hybrid Cu/dielectric wafer-to-wafer bonding" @default.
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- W2499888942 doi "https://doi.org/10.1109/itherm.2016.7517703" @default.
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