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- W2500854597 abstract "We study the scaling properties of self-aligned InGaAs FinFETs with sub-10-nm fin widths fabricated through a CMOS compatible front-end process. Working devices with fins as narrow as 7 nm, fin aspect ratios in excess of 5, and gate lengths as short as 20 nm have been fabricated using precision dry etching and digital etch. The devices feature self-aligned metal contacts that are 20-30 nm away from the edge of the gate. FinFETs with L <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>g</sub> = 30 nm, W <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>f</sub> = 7 nm, and channel height of 40 nm exhibit a transconductance of 900 μS/μm at V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>DS</sub> = 0.5 V. When normalized to W <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>f</sub> , this is a record value among all III-V FinFETs, indicating that our device architecture makes efficient use of conduction along the fin sidewalls." @default.
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- W2500854597 date "2016-09-01" @default.
- W2500854597 modified "2023-09-27" @default.
- W2500854597 title "Sub-10-nm Fin-Width Self-Aligned InGaAs FinFETs" @default.
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- W2500854597 doi "https://doi.org/10.1109/led.2016.2596764" @default.
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