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- W2501971876 abstract "In this paper, we propose a hardware accelerator for computing 3-D DFT. This architecture implements split radix-2/4 DIF FFT algorithm. The accelerator is a controller-based architecture where the host processor moves the data to the local memory of the accelerator. The accelerator minimizes memory accesses, cost and critical path, and increases efficiency of the processor. The architecture is designed to be used in medical image processing applications like MRI." @default.
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- W2501971876 date "2008-02-06" @default.
- W2501971876 modified "2023-09-24" @default.
- W2501971876 title "Hardware accelerator for computing 3-D DFT in medical image processing" @default.
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