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- W2503963721 abstract "This paper describes a single-ended switch-capacitor harmonic-rejection power amplifier to operate in the 915 MHz ISM band for ZigBee applications. A multipath feed-forward harmonic-rejection technique is employed to suppress the 2nd/3rd/4th harmonics of the switch-capacitor power amplifier (PA) by 48/17/24 dB, respectively. The measured PA peak drain efficiency is 43% at a peak output power of 8.9dBm with the harmonic-rejection enabled. This PA was implemented in a 40nm TSMC CMOS process with an active area of 180μm×700μm." @default.
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- W2503963721 date "2016-05-01" @default.
- W2503963721 modified "2023-09-26" @default.
- W2503963721 title "A 40nm CMOS single-ended switch-capacitor harmonic-rejection power amplifier for ZigBee applications" @default.
- W2503963721 cites W1981305442 @default.
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- W2503963721 doi "https://doi.org/10.1109/rfic.2016.7508289" @default.
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