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- W2504828303 abstract "This chapter presents research efforts in the related areas of communication architecture refinement and interface synthesis. Communication architecture refinement is an essential part of any system-on-chip (SoC) design flow, as high level models are iteratively refined with more detail being added, till an implementation model is obtained. Models at different levels of abstraction are required because each abstraction level possesses its own unique advantages and disadvantages; for example, high-level models enable faster simulation but less accuracy, while lower level models have greater accuracy, but suffer from slow simulation speeds due to the large amount of captured detail. Several research efforts are presented that facilitate the task of creating interface logic for interfacing components at different abstraction levels and for rectifying mismatches in protocols used by two or more components, so that the system works correctly, as intended. Finally, the chapter discusses some work in the area of interface optimization to improve application performance by using latency reducing techniques during the design of component interfaces." @default.
- W2504828303 created "2016-08-23" @default.
- W2504828303 creator A5018382547 @default.
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- W2504828303 date "2008-01-01" @default.
- W2504828303 modified "2023-10-14" @default.
- W2504828303 title "On-Chip Communication Architecture Refinement and Interface Synthesis" @default.
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- W2504828303 doi "https://doi.org/10.1016/b978-0-12-373892-9.00009-8" @default.
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