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- W2508895833 abstract "This paper presents a high-level synthesis system, called RMAC-V (Reconfigurable Machine Application Compiler for RM-V), for applications using SDRAMs implemented on the flexible architecture of RM-V (Re-configurable Machine-V) combining FPGAs and memories. Given an application program written in the C language, RMAC-V produces an RT-level hardware description in VHDL. To reduce the clock counts needed to access memories, RMAC-V introduces two techniques: multi-clock scheduling and preloading row address. Experimental results on Wavelet Transform Engine (WTE) have shown 33% fewer total clock counts than those with conventional method." @default.
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- W2508895833 date "2000-01-01" @default.
- W2508895833 modified "2023-09-23" @default.
- W2508895833 title "A High-Level Synthesis System for Reconfigurable Machine: RM-V" @default.
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- W2508895833 doi "https://doi.org/10.1541/ieejeiss1987.120.11_1637" @default.
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