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• W2509603387 abstract "A system-on-a-chip (SoC) requires several phase-locked loops (PLLs) for providing different clock frequencies to different modules. Usually, analog PLLs cannot be stopped due to their long setting time. Hence, these PLLs dominate the system's standby power consumption. In this paper, a fast lock-in all-digital PLL (ADPLL) that can achieve lock-in within 4.5 clock cycles is proposed to ensure that it can be switched off in the low power mode. The output frequency of the proposed ADPLL ranges from 125 MHz to 1.47 GHz, and the power consumption is 0.98 mW (at 0.9 V, 1.47 GHz)." @default.
• W2509603387 created "2016-09-16" @default.
• W2509603387 creator A5004614343 @default.
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• W2509603387 date "2016-01-01" @default.
• W2509603387 modified "2023-09-24" @default.
• W2509603387 title "A fast lock-in all-digital phase-locked loop in 40-nm CMOS technology" @default.
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• W2509603387 doi "https://doi.org/10.1587/elex.13.20160749" @default.
• W2509603387 hasPublicationYear "2016" @default.
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