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• W2514212912 abstract "The reduction in feature size increases the probability of manufacturing defect in the IC will result in a faulty chip. A very small defect can easily result in a faulty transistor or interconnecting wire when the feature size is less. Testing is required to guarantee fault-free products, regardless of whether the product is a VLSI device or an electronic system. Simulation is used to verify the correctness of the design. To test n input circuit we required 2 n test vectors. As the number inputs of a circuit are more, the exponential growth of the required number of vectors takes much time to test the circuit. It is necessary to find testing methods to reduce test vectors . So here designed an heuristic approach to test the ripple carry adder. Modelsim and Xilinx tools are used to verify and synthesize the design." @default.
• W2514212912 created "2016-09-16" @default.
• W2514212912 creator A5038712387 @default.
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• W2514212912 date "2016-08-30" @default.
• W2514212912 modified "2023-09-27" @default.
• W2514212912 title "Design Verification and Test Vector Minimization Using Heuristic Method of a Ripple Carry Adder" @default.
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• W2514212912 doi "https://doi.org/10.5121/ijci.2016.5433" @default.
• W2514212912 hasPublicationYear "2016" @default.
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