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• W2514307950 abstract "Current TSV integration schemes include via-first, via-middle and via-last process flows. In this paper, a low thermal budget, 10ìm pitch and aspect ratio 10 (5ìm diameter, 50ìm depth) via-last TSV module is presented. The proposed via-last module is plugged in after the thinning module, with 50ìm thinned device wafers temporary bonded to a Si carrier, using Brewer Science Zonebond® material. After the deposition of a thin back side passivation layer, the TSV lithography is performed with back-to-front alignment to the front side Metal1 pattern using a Dual Side Alignment (DSA) system, available on the Ultratech AP300. The overlay performance to Metal1, verified by dedicated software utilizing the DSA alignment system, is better than 750nm, fulfilling the requirements for a 5ìm diameter by 50ìm depth TSV module with a TSV pitch of 10ìm. The TSV deep-Si etch lands on the STI/PMD oxide stack. In order to prevent severe notching at the silicon to oxide interface, a soft landing etch step is introduced by tuning the etch process parameters. The soft landing accommodates as well for the total silicon thickness variation of the thinned wafers. Prior to the TSV resist strip, the STI and PMD oxide is etched, stopping just above the Metal1 landing pads. Next, a high conformal PEALD oxide liner is deposited at low temperature, avoiding local deformation of the thermoplastic temporary glue material. In order to enable electrical contact from the TSV to the Metal1 landing pads, the liner oxide is selectively removed at the bottom of the TSV by means of a directional dry etch step. To avoid any liner oxide recess at the top of the TSV, the liner is protected with a non-conformal PECVD low temperature SiN layer. This SiN layer deposits at the top part of the TSV, capping the oxide liner, but doesn't deposit deeper into the TSV. As a result, the oxide liner is cleared at the TSV bottom during the oxide liner etch, at the same time preserving this oxide liner at the top of the TSV which is protected by the PECVD SiN capping layer. Prior to the PVD Ta barrier deposition, a dedicated argon soft sputter etch with high RF bias power is applied to ensure the complete removal of any tantalum oxide interfacial layer. The PVD Cu seed is deposited in-situ with the barrier. ECD copper fill and CMP of the Cu overburden and Ta barrier material finishes the via-last module. Backside RDL, using a semi-additive process, provides the electrical contact to the TSV at the thinned wafer back side. Electrical results are shown, proving the maturity of this TSV last process scheme. The connectivity of the TSV, from wafer front to back side, has been checked by means of kelvin and daisy chain structures, showing 100% yield and low spread on the measured resistance values. Low leakage current and high breakdown voltage of the TSVs is obtained, demonstrating the integrity of the oxide liner all over the TSV sidewall." @default.
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• W2514307950 date "2016-05-01" @default.
• W2514307950 modified "2023-10-02" @default.
• W2514307950 title "Small Pitch, High Aspect Ratio Via-Last TSV Module" @default.
• W2514307950 cites W2080281774 @default.
• W2514307950 doi "https://doi.org/10.1109/ectc.2016.155" @default.
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