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- W2516744640 abstract "This paper presents a successive-approximation-register (SAR) analogue-to-digital converter (ADC) using a tri-level switching scheme named as reverse VCM-based scheme which maintains good linearity without any driving and accuracy requirements on VCM. A 10-bit SAR ADC is designed in a 0.18 CMOS technology. With a unit capacitor size of 17.2 fF, the ADC consumes 41.9 μW from a 1.8 V voltage supply. The measured signal-to-noise-plus-distortion ratio (SNDR) is 59.6 dB at 2 MS/s. The figure-of-merit (FOM) is 26.9 fJ/conv.-step." @default.
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- W2516744640 date "2016-05-01" @default.
- W2516744640 modified "2023-09-22" @default.
- W2516744640 title "A 10-bit 2 MS/s SAR ADC using reverse VCM-based switching scheme" @default.
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- W2516744640 doi "https://doi.org/10.1109/iscas.2016.7527419" @default.
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