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- W2517023266 abstract "In this paper, a low power 5-bit hybrid flasharchitecture is proposed. The proposed analog-to-digital con-verter (ADC) uses appropriate combination of both conventionaldouble-tail comparators and standard cell comparators. Stan-dard cell comparators are used to reduce power consumption. Thus, the proposed hybrid architecture results in extendeddynamic range when compared to standard cell and thresholdinverter quantization (TIQ) based flash ADC. The proposedhybrid architecture is implemented in CMOS 180 nm N-welltechnology with 1.8 V supply. Simulation results show thepower reduction upto 48.47% when compared to conventionalarchitecture. The simulated spurious-free dynamic range (SFDR) is 38.54 dB and effective number of bits (ENOB) is 4.7 bits witha 1.22 MHz input at a sampling rate of 250 MS/s. The hybridADC consumes about 7.11 mW of power with figures of merit(FOM) of 1094.18 fJ/conversion-step." @default.
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- W2517023266 date "2016-07-01" @default.
- W2517023266 modified "2023-09-25" @default.
- W2517023266 title "Design of Low Power 5-Bit Hybrid Flash ADC" @default.
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- W2517023266 doi "https://doi.org/10.1109/isvlsi.2016.53" @default.
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