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• W2517523927 abstract "With the number of IP cores in a multicore system-on-chip increasing to up to tens or hundreds, the role of on-chip interconnection networks is vital. We propose a networks-on-chip-style bus network as a compromise and redefine the exploration problem to find the best IP tiling patterns and communication path combinations. Before solving the problem, we estimate the time complexity and validate the infeasibility of the solution. To reduce the time complexity, we propose two fast exploration algorithms and develop a program to implement these algorithms. The program is executed for several experiments, and the exploration time is reduced to approximately 1/22 and 7/1,200 at the first and second steps of the exploration process, respectively. However, as a trade-off for the time saving, the time cost (TC) of the searched architecture is increased to up to 4.7% and 11.2%, respectively, at each step compared with that of the architecture obtained through full-case exploration. The reduction ratio can be decreased to 1/4,000 by simultaneously applying both the algorithms even though the resulting TC is increased to up to 13.1% when compared with that obtained through full-case exploration." @default.
• W2517523927 created "2016-09-16" @default.
• W2517523927 creator A5037444709 @default.
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• W2517523927 date "2016-12-01" @default.
• W2517523927 modified "2023-09-25" @default.
• W2517523927 title "Design Space Exploration for NoC-Style Bus Networks" @default.
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• W2517523927 doi "https://doi.org/10.4218/etrij.16.0116.0037" @default.
• W2517523927 hasPublicationYear "2016" @default.
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