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• W2522116871 abstract "In modern system-on-chip architectures, specialized accelerators are increasingly used to improve performance and energy efficiency. The growing complexity of these systems requires the use of system-level design methodologies featuring high-level synthesis (HLS) for generating these components efficiently. Existing HLS tools, however, have limited support for the system-level optimization of memory elements, which typically occupy most of the accelerator area. We present a complete methodology for designing the private local memories (PLMs) of multiple accelerators. Based on the memory requirements of each accelerator, our methodology automatically determines an area-efficient architecture for the PLMs to guarantee performance and reduce the memory cost based on technology-related information. We implemented a prototype tool, called Mnemosyne, that embodies our methodology within a commercial HLS flow. We designed 13 complex accelerators for selected applications from two recently-released benchmark suites (Perfect and CortexSuite). With our approach we are able to reduce the memory cost of single accelerators by up to 45%. Moreover, when reusing memory IPs across accelerators, we achieve area savings that range between 17% and 55% compared to the case where the PLMs are designed separately." @default.
• W2522116871 created "2016-09-30" @default.
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• W2522116871 date "2016-01-01" @default.
• W2522116871 modified "2023-10-18" @default.
• W2522116871 title "System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip" @default.
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• W2522116871 doi "https://doi.org/10.1109/tcad.2016.2611506" @default.
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