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• W2524065902 abstract "We report the first demonstration of InGaAs/SiGe CMOS inverters and dense SRAM arrays on Si, fabricated with InGaAs selective epitaxy and standard front end of line (FEOL) processes. This novel and scalable CMOS integration scheme enables InGaAs nFET fabrication in close proximity to SiGe pFETs (down to 25 nm spacing), resulting in 6T-SRAM arrays having a minimum cell size below 0.45 µm2. This scheme can be combined with any bulk Si or SOI-based planar or fin technology, and is compatible with standard large-area Si substrate. Individual InGaAs nFETs and SiGe pFETs are fabricated with a standard self-aligned CMOS-compatible process flow and feature L G scaled down to 35 nm. Moreover, the InGaAs nFET process flow includes selective epitaxy, raised source/drain (RSD) and high-k/metal gate (HKMG) modules. Finally, we report electrical characterization of isolated FETs and inverters as well as dense SRAM cells with planar and fin- FETs." @default.
• W2524065902 created "2016-10-07" @default.
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• W2524065902 date "2016-06-01" @default.
• W2524065902 modified "2023-10-16" @default.
• W2524065902 title "First demonstration of InGaAs/SiGe CMOS inverters and dense SRAM arrays on Si using selective epitaxy and standard FEOL processes" @default.
• W2524065902 doi "https://doi.org/10.1109/vlsit.2016.7573391" @default.
• W2524065902 hasPublicationYear "2016" @default.
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