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- W2525375610 abstract "In next generation wireless communication system, wireless transceivers should be able to handle wideband input signals compromising of multiple communication standards.Such multi-standard wireless communication receivers (MWCRs) need filter bank to extract the desired signal of interest from wideband input spectrum and bring it to the baseband for further signal processing tasks such as spectrum sensing, modulation classification,demodulation etc.In MWCRs,rather any wireless receivers, modulated filter banks, such as Discrete Fourier Transform Filter Banks (DFTFB), are preferred due to their advantages such as lower area, delay and power requirements. To support multi-standard operation, reconfigurable DFTFB (RDFTFB) was proposed by integrating DFTFB with the coefficient decimation method. In this paper, an efficient high speed implementation of RDFTFB on Virtex-7 field programmable gate arrays (FPGA) has been proposed.The proposed approach minimizes the critical path delay between clocked registers thereby leading to significant improvement in the maximum operating frequency of the RDFTFB. Numerically, the proposed implementation leads to 89.7% improvement in the maximum frequency at which RDFTFB can be clocked.Furthermore,proposed implementation leads to 18.5% reduction in the dynamic power consumption." @default.
- W2525375610 created "2016-10-07" @default.
- W2525375610 creator A5038946739 @default.
- W2525375610 creator A5084951491 @default.
- W2525375610 date "2016-09-15" @default.
- W2525375610 modified "2023-09-26" @default.
- W2525375610 title "FPGA Implementation of High Speed Reconfigurable Filter Bank for Multi-standard Wireless Communication Receivers" @default.
- W2525375610 cites W2009207934 @default.
- W2525375610 cites W2100575086 @default.
- W2525375610 cites W2110702117 @default.
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- W2525375610 doi "https://doi.org/10.48550/arxiv.1609.08192" @default.
- W2525375610 hasPublicationYear "2016" @default.
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