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• W2532110055 abstract "Nowadays, during the digital systems design process, several steps are involved; one of the most important is design verification. The verification represents the biggest part of the total manufacturing cost of the devices. The approximated cost of this phase is estimated at about 70% of the total cost of the digital system design. On the other hand, unlike software, the errors in hardware design are very expensive, because this requires redesigning and physically replacing the failed device. Also, because of the increase in the complexity of digital systems lately, the importance of creating efficient designs and reducing their verification time has generated the need to create more efficient design verification techniques that reduce the time and increase the test coverage percentage. Different methods have been developed to perform the verification processes, also new software tools have been produced. However, these software platforms have been used with different digital systems, and the results obtained show that it is necessary to develop more efficient methods that can cover the hardest design cases. The task of cheking all input vectors in the device is infeasible because the coverage space is increased when the complexity of the device is bigger. Generally, the main objective of the informal verification techniques is to increase design space coverage and changes for finding errors in the digital systems design. When the verification of an implemented device is performed in a hardware description language (Verilog, VHDL, Systemverilog), the verification engineer needs to use specialized software tools (Questa, Modelsim, Cadence). The directed functional verification has an important role to meet with the conditions. There has been detected that there is infectivity when the pseudo random test generation methods to cover hard cases, it is necessary to propose new test vector generation methods. When the functional verification is performed, a coverage model is used. This model is based on a type of coverage structure or coverage metric, i.e., finite state machine (FSM), statement, branch path, and expression coverage etc. This coverage model is a fundamental piece for the method representing a golden model to describe the device behavior. There are different ways to close the loop between the end of simulation and the new generation of tests has been proposed. The coverage directed test generation (CDG) has been proposed as a possible solution to this problem. Different experiments have shown that the directed probes are promising because a small number of them can reach the same coverage goal with respect to the constrained random probes. In this work we proposed a new method which uses reduced meta-heuristic versions to generate a set of vector sequences. The method tests the hardest design cases. We focus on the hybrid methods (based on the simulation) since these methods have obtained good results even though there is an increase in digital systems complexity. The strategy employed is based on the use of coverage models for the devices verification process, which are built with relevant conditions or coverage points representing the device under verification (DUV) full behavior. The main problem consists in covering all hard cases since the relationships between the test points and the input data at the design are not trivial. Different to the previous works that used heuristics, the proposed method can reduces the number of evaluations used to obtain test sequences that exercise the coverage points. Due to the fact that relationships between the inputs and the relevant events or conditions are not trivial when the verification is performed, there are very difficult cases to test during the verification of a digital system. If the coverage directed test generation is applied, sets of holes are detected at the end of the simulation and one or more conditions need to be tested in the new iteration. This means that the main problem consists in obtaining high values to exercise all functional coverage events in the device. This problem is currently under search and has been found difficult to solve due to the increase of functional complexity circuits. To solve the problem we propose a new method based on micro-versions of meta heuristics. Different from previous works, the main idea is to use simplified heuristic methods by means of an efficient use of the coverage space. This means that the proposed method obtains high coverage percentages with a low simulation cost. The main strategy consists in dividing the coverage model into sets of hardest coverage points and use appropriate cost functions to test these points and combine meta-heuristics to create a hybrid heuristic which increases the obtained percentages. There has been little work carried out on techniques for hardware verification based on heuristics. There are some works that have been used meta-heuristics like genetic algorithms. However, there are more efficient optimizer heuristic techniques, e.g. Differential Evolution (DE) algorithm, Particle Swarm Optimization (PSO) algorithm, and also this work differs in that the method proposed uses combinations of micro-versions of the meta-heuristics (BinDE, BinPSO) in the binary domain. In the case of both algorithms, these have been used in different optimization problems. The test vectors generator module uses these algorithms to obtain test vector sequences that cover all coverage points. On the other hand, this hybrid method uses a verification platform that we have proposed. The verification platform is constructed by a C-Systemverilog interface, which connects the DUV with the C files used for the different algorithms interacting in the method. When the simulation is performed, a set of statistic information is generated which includes: a) the percentages obtained by the coverage points; b) the number of evaluations; c) best, worst and average percentages; c) configuration; d) number of errors found; d) best solutions in each experiment as saved in the files. This information is used to build sets of different hard points and propose some cost functions for the optimization algorithms. The proposed method is based on a functional verification model, which includes coverage points to perform the coverage directed verification. The method generates sets of vectors through the use of the Particle Swarm Optimization algorithm and the Differential Evolution algorithm. Figure 1 shows the proposed method used in this research. To configure the size of test vector sequences, it is necessary to review the functional specification. With respect to the meta-heuristics: a) a number of iterations is proposed as a stop criterion; b) a percentage value. At the end of the simulation the coverage information is analyzed and that information is taken by the heuristic to produce new test sequences. The experiments were performed using the verification platform on the Fedora Core Linux operating system. The devices used to perform the functional verification are a synchronous FIFO memory (It is a common device which can be part of more complex devices such as an UART, a microprocessor etc.) and a UART-bus IP core, in which different coverage points were selected. In the case of the UART-bus IP core, this can be used during initial board debugging, or as a permanent solution when high speed interfaces are not required. The internal bus is designed with an address bus of 16 bits and a data bus of 8 bits. The core implements a transmitted and a received block which share a common baud rate generator and a command parser. The parser supports two modes of operation: text mode and binary mode commands. Different scenarios to test the method were used in the experiments. The velocity, number of particles and neighborhood numbers were changed. The configuration version of PSO algorithm was lbest and gbest for each scenario. This means that the configuration of the binary Particle Swarm Optimization algorithm was different in each scenario. The main contribution of this work is that the method can obtain a set of test vector sequences to achieve high values based on the coverage directed test generation process. The information is evaluated based on the sets of holes obtained during this process. This allows the method to focus on specify cases and finally join the vector sequences." @default.
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• W2532110055 date "2014-10-01" @default.
• W2532110055 modified "2023-09-24" @default.
• W2532110055 title "Automated functional coverage directed for complex digital systems" @default.
• W2532110055 doi "https://doi.org/10.1109/vlsi-soc.2014.7004172" @default.
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