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- W2532850133 abstract "In this paper, CAD models of the input admittance of RC interconnects are discussed. To this aim, properties of RC circuits are exploited to show that the input admittance of RC wires is approximated very well by that of a low order RC circuit, as opposite to the timing modeling of RC wires. In particular, 1 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>st</sup> - or 2 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>nd</sup> -order equivalent circuits are shown to be sufficient for fast and accurate estimations of the loading effects associated with RC wires. The accuracy of these models is evaluated and compared in various practical situations that occur in automated design flows, i.e. in the evaluation of the main timing/power parameters of buffers loaded by an RC wire (e.g., delay, peak supply current, ...). This allows for understanding the suitability of each model for fast and accurate estimations of the loading effects of RC wires on buffers. Finally, a simple criterion to select the most suitable model of these loading effects is proposed for each parameter of interest in current CAD tools for VLSI design." @default.
- W2532850133 created "2016-10-28" @default.
- W2532850133 creator A5052037141 @default.
- W2532850133 date "2008-12-01" @default.
- W2532850133 modified "2023-09-26" @default.
- W2532850133 title "CAD models of the input admittance of RC wires: Comparison and selection strategies" @default.
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- W2532850133 doi "https://doi.org/10.1109/icm.2008.5393515" @default.
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