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• W2533622023 abstract "The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. In this context, it has been proven that Single Input Change (SIC) test sequences are more effective than classical Multiple Input Change (MIC) test sequences when a high robust delay fault coverage is targeted In this paper, we show that random SIC (RSIC) test sequences achieve a higher fault coverage than random MIC (RMIC) test sequences when both robust and non-robust tests are under consideration. Experimental results given in this paper are based on a software generation of RSIC test sequences that can be easily generated in this case. For a built-in self-test (BIST) purpose, hardware generated RSIC sequences have to be used. This kind of generation is briefly discussed." @default.
• W2533622023 created "2016-10-28" @default.
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• W2533622023 date "2002-11-07" @default.
• W2533622023 modified "2023-09-25" @default.
• W2533622023 title "Delay fault testing: choosing between random SIC and random MIC test sequences" @default.
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• W2533622023 doi "https://doi.org/10.1109/etw.2000.873772" @default.
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