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• W2533829917 abstract "An issue-oriented architecture designed for high performance is described. It uses features, such as simple instruction formats, large number of registers, and load/store architecture, found in some reduced-instruction-set-computer architectures. It also includes features, such as out-of-order completion, imprecise exceptions, and vector processing, found in supercomputers such as the CRAY-1. Furthermore, it provides a full set of system support features, such as multiprocessor synchronization, vectored exceptions, stacks, asynchronous system traps, and extensive memory management, found in complex architectures such as the VAX. The reduced instruction parallel/pipelined (RIP) architecture is described. The RIP architecture was designed as a robust architecture to meet a wide range of system requirements across a family of implementations. The processor model that guided the architecture definition consists of multiple pipelined function units, each of which executes a class of instructions. >" @default.
• W2533829917 created "2016-10-28" @default.
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• W2533829917 date "2002-12-04" @default.
• W2533829917 modified "2023-09-23" @default.
• W2533829917 title "High performance issue oriented architecture" @default.
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• W2533829917 doi "https://doi.org/10.1109/cmpcon.1990.63667" @default.
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