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- W2534319480 abstract "Summary form only given. Our work alms to accelerate FPGA application development by raising the level of abstraction and facilitating design reuse. We propose a solution based on network of nodes, communicating using a packet-based protocol. This network of nodes is known as customisable modular platform (CMP). A node is a computational unit, which can be hardware core running on an FPGA, or a thread running on a processor or a DSP. Hardware nodes can span over several FPGAs or there can be several nodes on a single FPGA. The packet-based communication protocol is implemented using an interchangeable interface. This interface provides a seamless data interchange between the nodes, independent of the implementation target architecture or abstraction. The communication packets of this protocol include control information and data, i.e. header and payload." @default.
- W2534319480 created "2016-10-28" @default.
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- W2534319480 date "2005-03-31" @default.
- W2534319480 modified "2023-09-27" @default.
- W2534319480 title "Reduction of design complexity using virtual hardware platforms" @default.
- W2534319480 doi "https://doi.org/10.1109/issoc.2004.1411151" @default.
- W2534319480 hasPublicationYear "2005" @default.
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