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• W2534484071 abstract "The proposed paper shows the half adder circuit with low power consumption preferred for arithmetic operations. Leakage power dissipation problem of electronics systems has attracted a lot of attention from engineers and researchers over the years. In the CMOS circuits Power dissipation occurs due to increasing leakage current in deep-sub micrometer regimes which is becoming a significant contributor as threshold voltage, channel length, and gate oxide thickness are reduced. The half adder circuit composed of XOR gate and AND logic gate, which have many transistor. Power consumption (leakage power) in the CMOS technology half adder circuit achieving better performance for maintain the speed, power dissipation, size, reliability of the device. SVL (Self-controllable Voltage Level) technique provides better leakage power reduction with minimum area and it not only reduces power but also retains data during standby period in half adder. Simulation work has been done in 45 nm technology, in this technology power consumption (leakage power) have provided for half adder circuit." @default.
• W2534484071 created "2016-10-28" @default.
• W2534484071 creator A5038669516 @default.
• W2534484071 creator A5088321782 @default.
• W2534484071 date "2014-11-01" @default.
• W2534484071 modified "2023-09-25" @default.
• W2534484071 title "Standby and active leakage current control mechanism of half adder cell" @default.
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• W2534484071 doi "https://doi.org/10.1109/cipech.2014.7019091" @default.
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