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- W2534707923 abstract "The logic construction of a double-edge-triggered (DET) flipflop, which can receive input signal at two levels of the clock, is analyzed and a new circuit design of CMOS DET flip-flop is proposed. Simulation using SPICE and a 1 micron technology shows that this DET flip-flop has ideal logic functionality, a simpler structure, lower delay time and higher maximum data rate compared to other existing CMOS DET flip flops. By simulating and comparing the proposed DET flip-flop with the other designs present, it is shown that the proposed DET flip-flop reduces power dissipation while keeping the same date rate and can be used for high speed applications." @default.
- W2534707923 created "2016-10-28" @default.
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- W2534707923 date "2016-10-17" @default.
- W2534707923 modified "2023-09-30" @default.
- W2534707923 title "Robust Design of a Dual Edge Triggered Flip Flop at Low Power for High Speed Applications" @default.
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- W2534707923 doi "https://doi.org/10.5120/ijca2016911930" @default.
- W2534707923 hasPublicationYear "2016" @default.
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