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• W2535084046 abstract "To keep pace with scaled technology and the requirements of SRAM for embedded high speed microprocessor cache, we use borderless contacts with an Al/sub 2/O/sub 3/ etch-stop and a combination of damascene and metal RIE local interconnect to achieve bulk 6T CMOS SRAM cell sizes from 34 to 15 /spl mu/m/sup 2/ (2-->4 Mb). The Al/sub 2/O/sub 3/ etch stop is RIE etched allowing the simultaneous formation of dense borderless contacts and low-resistance local interconnect, unlike previous approaches that wet etch the Al/sub 2/O/sub 3/. We have fabricated 64 K CMOS SRAMs with 5 ns access time suitable for 2 Mb embedded 2.5 V, 0.25 pm L/sub EFF/ SRAM technology using salicide, oxide planarization, dry etched Al/sub 2/O/sub 3/ etch stop, W damascene local interconnect layer, and two level AlCu metal. We have extended this technology to 4 Mb SRAM cells using a polycide gate stack damascene MO with contact to diffusion that is borderless to both gate and isolation edges, a second metal RIE local interconnect, and using a scaled device design. >" @default.
• W2535084046 created "2016-10-28" @default.
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• W2535084046 date "2002-12-30" @default.
• W2535084046 modified "2023-09-26" @default.
• W2535084046 title "A novel borderless contact/interconnect technology using aluminum oxide etch stop for high performance SRAM and logic" @default.
• W2535084046 cites W1896357171 @default.
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• W2535084046 doi "https://doi.org/10.1109/iedm.1993.347315" @default.
• W2535084046 hasPublicationYear "2002" @default.
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