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- W2536204089 abstract "3DVLSI is an emerging more than Moore technology. In this paper, we propose 3D design methodologies dealing with process variability. Using SPICE models and Monte Carlo simulations we show a delay partioning method for stacked circuits to reduce frequency dispersion by 30%. We also compare how the process correlation between tiers influences the design corners." @default.
- W2536204089 created "2016-10-28" @default.
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- W2536204089 date "2016-09-01" @default.
- W2536204089 modified "2023-09-25" @default.
- W2536204089 title "Delay partitioning helps reducing variability in 3DVLSI" @default.
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- W2536204089 doi "https://doi.org/10.1109/esscirc.2016.7598246" @default.
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