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- W2536435918 abstract "The continued scaling of Si MOSFET faces many critical issues. In this paper, the authors discuss drain architecture in relation to performance and the possibility of sub-0.1 /spl mu/m CMOS devices. It is found that an abrupt junction is indispensable for source/drain (S/D) extension to obtain higher drain current capability. On the other hand, a graded junction is desirable for deep S/D to decrease the junction capacitance. The drain architecture combined with doping technology such as plasma doping and spike anneal is one of the most important solutions for sub-0.1 /spl mu/m MOSFETs." @default.
- W2536435918 created "2016-10-28" @default.
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- W2536435918 date "2003-01-22" @default.
- W2536435918 modified "2023-09-24" @default.
- W2536435918 title "CMOS device technology toward 50 nm region-performance and drain architecture" @default.
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- W2536435918 doi "https://doi.org/10.1109/iedm.1999.824234" @default.
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