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- W2536599140 abstract "This paper presents a high-performance low-power 2D IDCT processor for video applications. Based on multiply-accumulator architecture, the processor can meet the high-speed requirement of HDTV. To save power consumption, the processor employs asynchronous pipeline in which local clocks are enabled only when there is an operation to perform. Compared with conventional synchronous pipelined design, the proposed design exhibits an average power saving of 40%." @default.
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- W2536599140 date "2006-04-07" @default.
- W2536599140 modified "2023-09-23" @default.
- W2536599140 title "A High-Performance Low-Power 2-D 8 X 8 IDCT Processor with Asynchronous Pipeline" @default.
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- W2536599140 doi "https://doi.org/10.1109/icasic.2005.1611307" @default.
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