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• W2536877045 abstract "In this paper a new capacitor-over-bit line (COB) cell for 1G DRAM is proposed. The cell area of 0.375 /spl mu/m/sup 2/ was obtained with diagonal bit line (DBL) configuration. An edge operation MOS (EOS) transfer gate has been developed which provides SOI-like small S-factor and V/sub TH/-V/sub SUB/ dependence. A storage capacitance of 28.5 fF was achieved with a Ta/sub 2/O/sub 5/ dielectric film on a hemispherical grain Si (HSG) cylinder structure. >" @default.
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• W2536877045 date "2002-12-17" @default.
• W2536877045 modified "2023-09-27" @default.
• W2536877045 title "1G DRAM cell with diagonal bit-line (DBL) configuration and edge operation MOS (EOS) FET" @default.
• W2536877045 cites W2100045218 @default.
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• W2536877045 doi "https://doi.org/10.1109/iedm.1994.383329" @default.
• W2536877045 hasPublicationYear "2002" @default.
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