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• W2538934675 abstract "En esta tesis hemos identificado tres de los mayores cuellos de botella para el rendimiento y escalabilidad de las arquitecturas many-core CMP de memoria compartida. En particular, los mecanismos de sincronizacion de barrera y cerrojo cuando presentan alta contencion, asi como los protocolos hardware de coherencia de cache en el mantenimiento de la coherencia del uso de bloques memoria compartidos en una jerarquia de memoria. Para paliar estas deficiencias y aprovechar mas el rendimiento de estas arquitecturas, hemos propuesto tres mecanismos hardware: GBarrier, para un mecanismo de barreras eficiente; GLock, para un manejo justo y eficiente de la contencion en el acceso a las secciones criticas protegidas por cerrojos; y ECONO, un protocolo de coherencia muy simple que aporta gran eficiencia a bajo costo. La tesis concluye que nuestras propuestas resuelven de manera eficiente los problemas de rendimiento derivados de implementaciones ineficientes para sincronizacion y coherencia en arquitecturas many-core CMP. Palabra clave de terminologia TESAURO 330406 ARQUITECTURA DE ORDENADORES In this thesis we have identified three of the major problems that restrict efficiency and scalability in future shared-memory tiled many-core CMPs. In particular, the synchronization operations of barriers and locks under highly-contended scenarios, and the hardware-based cache coherence protocols when dealing with the maintenance of coherence of all memory blocks across all levels of a memory hierarchy. To alleviate such performance bottlenecks in order to harness the computational power of such systems, we have proposed three hardware-based mechanisms: GBarrier, a very efficient barrier mechanism; GLock, an efficient and fair mechanism to implement highly-contended locks; and ECONO, a simple and efficient hardware coherence protocol. In light of our performance results obtained in this thesis, we can affirm that our proposals represent a step forward towards the resolution of the challenges that many-core CMP architectures will pose to computer architects. Palabra clave de terminologia TESAURO en ingles 330406 COMPUTER ARCHITECTURE" @default.
• W2538934675 created "2016-10-28" @default.
• W2538934675 creator A5068560393 @default.
• W2538934675 creator A5088892690 @default.
• W2538934675 date "2013-01-23" @default.
• W2538934675 modified "2023-09-28" @default.
• W2538934675 title "Sincronización y comunicación eficientes en arquitecturas many-core CMP = Efficient synchronization and communication in many-core chip multiprocessors" @default.
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