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- W2539374767 abstract "Flexibly-V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>th</sub> -controllable four-terminal-FinFETs (4T-FinFETs) (Fried, et al., 2003) have great potential to prevent catastrophic increases in static power consumption. Previously-reported 4T-FinFETs had symmetrically thin gate oxides on both channels, unfortunately resulting in large S-slope due to the negative effect of the high second gate (G2) controllability (Lim, et al., 1983). To attain a good S-slope even after DG separation, the asymmetric gate oxide thickness (T <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>ox</sub> ) (thin drive-gate oxide and slightly thick V <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>th</sub> -control-gate oxide) have been suggested. (Wong, et al., 1998) This paper demonstrates, for the first time, asymmetric-T <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>ox </sub> 4T-FinFETs with HfO <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sub> (EOT=1.4nm) for one side and HfO <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sub> +thick SiO <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sub> (EOT=6.4-9.4nm) for the other side fabricated by using a novel ion-bombardment-enhanced etching (IBEE) process" @default.
- W2539374767 created "2016-10-28" @default.
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- W2539374767 date "2006-10-01" @default.
- W2539374767 modified "2023-09-30" @default.
- W2539374767 title "Demonstration of Asymmetric Gate Oxide Thickness 4-Terminal FinFETs" @default.
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- W2539374767 doi "https://doi.org/10.1109/soi.2006.284489" @default.
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