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- W2539610281 abstract "We demonstrate a novel device concept, in which junctions (active regions in CMOS) are interleaved with dielectric regions (STI) in order to increase the junction breakdown voltage. Experiments performed in a standard 90 nm CMOS process show an increase in breakdown voltages of extended drain MOSFETs from 15 to 45 V. This approach gives designers an extra degree of freedom to integrate high voltages in any standard CMOS process by STI layout design only, without the need for process modifications." @default.
- W2539610281 created "2016-11-04" @default.
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- W2539610281 date "2006-04-07" @default.
- W2539610281 modified "2023-10-16" @default.
- W2539610281 title "Dielectric resurf: breakdown voltage control by STI layout in standard CMOS" @default.
- W2539610281 cites W2159961487 @default.
- W2539610281 doi "https://doi.org/10.1109/iedm.2005.1609354" @default.
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