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- W2541554020 abstract "A new buried channel PMOSFET structure by forming P+ poly-Si sidewall spacers next to the main N+ poly-Si gate electrode is proposed and developed for deep submicron applications. By using this new device structure, the current drivability of a 0.3 mu m PMOSFET is increased by about 40%. This significant increase in current drivability can be attributed to the parasitic resistance reduction due to the formation of P-type inversion layers under the two P+ poly-Si sidewall spacers. Because of the work function difference between the N+ poly-Si gate electrode and the P+ poly-Si spacers, the Si surface under the P+ poly-Si spacers is always more inverted than the channel. As a result, the parasitic resistance is always much lower than the channel resistance. Furthermore, those induced inversion layers act as ultra shallow junctions (<or=100AA), which are self aligned to the P+ poly-Si spacers. Further reduction in the short-channel effects can be expected.<<ETX>>" @default.
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- W2541554020 date "1992-01-01" @default.
- W2541554020 modified "2023-09-24" @default.
- W2541554020 title "High performance deep submicron buried channel PMOSFET using P/sup +/ poly-Si spacer induced self-aligned ultra shallow junctions" @default.
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- W2541554020 doi "https://doi.org/10.1109/iedm.1992.307503" @default.
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