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- W2542470870 abstract "Using two-dimensional simulations, the gate capacitances of n-channel, p-barrier GaAs junction field effect transistors (JFETs) fabricated with ion-implantation and diffused-junction technologies are analyzed. In addition to channel, fringe, and pad capacitances which are also present in GaAs MESFETs, JFETs have sidewall capacitances and a capacitance due to the effective increase in the gate length caused by the lateral spreading of the p dopants. Both of these capacitances can be minimized by reducing the depth of the p region. Sidewall capacitance can be nearly eliminated if the p region depth is less than the depth of the surface depletion in the n region beside the gate. The results are compared with RF data for ion-implanted JFETs.< <ETX xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>></ETX>" @default.
- W2542470870 created "2016-11-04" @default.
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- W2542470870 date "2003-01-02" @default.
- W2542470870 modified "2023-09-25" @default.
- W2542470870 title "Analysis of gate capacitances in GaAs JFETs" @default.
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- W2542470870 doi "https://doi.org/10.1109/gaas.1992.247263" @default.
- W2542470870 hasPublicationYear "2003" @default.
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