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- W2543829088 abstract "The downscaling of transistor feature sizes has led to integrated circuits that are more susceptible to various fault effects. In order to meet dependability requirements, appropriate fault tolerance techniques have to be applied. This adds another challenging task to the design process of integrated circuits, which has to include a careful evaluation of costs and benefits of different fault-tolerant implementations. This paper presents a tool that supports this design space exploration by automatically evaluating the use of hardware redundancy-based fault tolerance for circuits specified in structural VHDL. The tool's main features as well as its integration in established EDA flows are described." @default.
- W2543829088 created "2016-11-04" @default.
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- W2543829088 date "2016-08-01" @default.
- W2543829088 modified "2023-09-30" @default.
- W2543829088 title "An Interactive Design Space Exploration Tool for Dependable Integrated Circuits" @default.
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- W2543829088 doi "https://doi.org/10.1109/dsd.2016.83" @default.
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