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- W2543967508 abstract "A 3-bit analog-to-digital converter (ADC) for software defined radio applications that can work at a sampling rate of 20 GS/s is presented in this paper. In order to operate at Ku-band, two flash current mode logic (CML) ADCs are time-interleaved to achieve a 20 GHz sampling rate. A 3-bit current-steering digital-to-analog converter (DAC) is also designed for testing the high-speed ADC. The ADC-DAC RFIC is implemented in a 0.12 mum SiGe technology and occupies an area of 1.5 times 1.7 mm <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>2</sup> . The total power consumption for the entire ADC-DAC chip is 2.36 W with a 4.2 V power supply. The ADC-DAC RFIC is packaged in a 44-pin CLLC package and achieves a peak spurious free dynamic range (SFDR) of 30.5 dBc and a peak effective number of bits (ENOB) of 2.8 bits at a 20 GS/s sampling rate." @default.
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- W2543967508 date "2007-11-01" @default.
- W2543967508 modified "2023-10-14" @default.
- W2543967508 title "A 3-bit 20GS/s interleaved flash analog-to-digital converter in SiGe technology" @default.
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- W2543967508 doi "https://doi.org/10.1109/asscc.2007.4425720" @default.
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