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- W2543977824 abstract "Two low-power, high-performance and low-clock-swing D Flip-Flops (DFFs), LN_TC_SA and LP_TC_SA, are proposed in this paper. These DFFs are extensively applicable as they utilize generic CMOS technology and need no additional power supply specially for the low clock swing sub-circuit by using two kinds of improved inverter designs. Simulation results show that the average leakage power and power delay product (PDP) of LNR_TC_SA are reduced by 65.00% and 11.38% respectively. Under 1.8 V supply, the proposed DFFs could still work even when the clock swing is as low as 647 mV, although at the expense of D-Q delay increase." @default.
- W2543977824 created "2016-11-04" @default.
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- W2543977824 date "2007-01-01" @default.
- W2543977824 modified "2023-10-16" @default.
- W2543977824 title "Low-Power, High-Performance and Low Clock Swing D Flip-Flops with Single Power Supply" @default.
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- W2543977824 doi "https://doi.org/10.1109/edssc.2007.4450260" @default.
- W2543977824 hasPublicationYear "2007" @default.
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