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- W2544670575 abstract "In recent years, there has been much discussion and effort expended in the area of Design-for-Testability with advances in fault modelling and test strategies such as the IEEE standard for scan test. This paper shows how the recognition of these trends led Schlumberger to introduce a new generation of VLSI testers which eases the design-to-test interface through the design of a new timing architecture which much more closely resembles the event-driven nature of simulator timing. Now designers are not limited by the necessity of having to run the simulator digital stimulus through a restrictive 'Tester Constraints' filter which is nearly always the case with the old format-style cycle-drive tester architecture. >" @default.
- W2544670575 created "2016-11-04" @default.
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- W2544670575 date "1991-05-16" @default.
- W2544670575 modified "2023-09-27" @default.
- W2544670575 title "Test for designability-a new architecture for VLSI testers" @default.
- W2544670575 hasPublicationYear "1991" @default.
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