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- W2545351010 abstract "This paper describes the design of a dual-channel optical transceiver array realized in a standard 0.18 mum CMOS technology for the applications of high-speed digital interface. The transmitter drives a 2-channel VCSEL array at 2.5 Gb/s, equipped with the APC (5-15 mA) and AMC (4-20 mA <sub xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>pp</sub> ) loops for constant and reliable optical power outputs. Meanwhile, the receiver exploits the common-gate transimpedance amplifier, demonstrating 87 dBOmega transimpedance gain, 1.4 GHz bandwidth for 2 pF input parasitic capacitance, -18 dBm sensitivity for 10 <sup xmlns:mml=http://www.w3.org/1998/Math/MathML xmlns:xlink=http://www.w3.org/1999/xlink>-12</sup> BER, and less than -20 dB crosstalk between TX and RX within the bandwidth. The whole 2-channel transceiver array chip dissipates 500 mW." @default.
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- W2545351010 date "2007-11-01" @default.
- W2545351010 modified "2023-09-27" @default.
- W2545351010 title "A 2.5Gb/s ESD-protected dual-channel optical transceiver array" @default.
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- W2545351010 doi "https://doi.org/10.1109/asscc.2007.4425754" @default.
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