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- W2546910098 abstract "A FIR filter for pre-emphasis has been used to counteract inter-symbol interference (ISI) in high-speed backplane data transmission. A novel circuit design for retiming data using a half-rate clock for the taps of a FIR filter is proposed. HSPICE simulation results for CMOS 0.18 mum technology verify that the jitter of PRBS15 (215 - 1) data at rate of 6.25 Gbps with a pre-emphasis value of 50% can be reduced to approximately 14 psec and thereby alleviating the requirement on clock frequency" @default.
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- W2546910098 date "2005-04-12" @default.
- W2546910098 modified "2023-09-27" @default.
- W2546910098 title "Symbol-spaced delay circuit design with half-rate clock timing for multi-taps FIR filter as pre-emphasis" @default.
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- W2546910098 doi "https://doi.org/10.1109/apccas.2004.1412763" @default.
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