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• W2547588325 abstract "This paper introduces CUSPARC-M, a many-core message-passing processor based on the Cairo University SPARC processor, CUSPARC, core. CUSPARC-M consists of 16 cores arranged in 4x4 mesh architecture. A Network-on-Chip (NoC) that incorporates X-Y routing, wormhole switching and dynamic virtual channels for flow control provides intra-chip communication. The design is synthesized using TSMC 65nm LP kit achieving power consumption of 13.68x and area of 17x compared to CUSPARC. The NoC consumes only 5.2% of the total power. Simulating a 16-block JPEG encoder on 12 cores of CUSPARCM yielded up to 8.72x speedup factor relative to the single-core version." @default.
• W2547588325 created "2016-11-11" @default.
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• W2547588325 date "2014-12-01" @default.
• W2547588325 modified "2023-09-27" @default.
• W2547588325 title "NoC-based many-core processor using CUSPARC architecture" @default.
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• W2547588325 doi "https://doi.org/10.1109/icm.2014.7071812" @default.
• W2547588325 hasPublicationYear "2014" @default.
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