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- W2548251230 abstract "A 100 Gb/s clock/data recovery circuit using a high-speed BiCMOS process is designed and simulated. In this circuit a half-rate 50 GHz clock signal, injected in parallel with the tail current of an LC VCO, locks to a 100 Gb/s input NRZ data signal. Inductive tuning for the frequency tuning of the VCO is employed, which gives a wide frequency tuning range while maintaining a constant quality factor." @default.
- W2548251230 created "2016-11-11" @default.
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- W2548251230 date "2016-06-01" @default.
- W2548251230 modified "2023-09-27" @default.
- W2548251230 title "A half-rate 100 Gb/s injection-locked clock/data recovery circuit" @default.
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- W2548251230 doi "https://doi.org/10.1109/newcas.2016.7604811" @default.
- W2548251230 hasPublicationYear "2016" @default.
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