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• W2550608975 abstract "In the context of industrial designs, circuits are based on many IPs defined on their own clock domain. It leads to globally asynchronous locally synchronous designs. The transmission of data between clock domains must be carefully verified to avoid metastability, inconsistency and data loss. EDA tools propose a strategy based on a minimal detection of a synchronizer structure. Conversely, in this paper we propose a meta-model of synchronizer that speeds up the proof and ensures its better automation." @default.
• W2550608975 created "2016-11-30" @default.
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• W2550608975 date "2016-10-01" @default.
• W2550608975 modified "2023-09-24" @default.
• W2550608975 title "Clock domain crossing formal verification: a meta-model" @default.
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• W2550608975 doi "https://doi.org/10.1109/hldvt.2016.7748267" @default.
• W2550608975 hasPublicationYear "2016" @default.
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