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- W2551072523 abstract "Although many built-in redundancy analysis (BIRA) algorithms which use parallel sub-analyzers have optimal repair rate and a fast analysis speed, they suffer from a large area overhead. To reduce the area overhead, a new BIRA analyzer is proposed which reconstructs the content addressable memory (CAM) structure of the parallel sub-analyzers like a binary searching tree. Experimental results show that the proposed BIRA analyzer achieves 25% reduction of area overhead compared with previous BIRA using parallel sub-analyzers in case an embedded memory has 4 spares with optimal repair rate and zero analysis speed." @default.
- W2551072523 created "2016-11-30" @default.
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- W2551072523 date "2009-01-01" @default.
- W2551072523 modified "2023-09-23" @default.
- W2551072523 title "An Advanced BIRA using parallel sub-analyzers for embedded memories" @default.
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- W2551072523 doi "https://doi.org/10.1109/socdc.2009.5423810" @default.
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