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- W2552045999 abstract "Dynamic critical path analysis in modern processors is needed to reduce margins typically determined by the static timing analysis. Dynamic path analysis, however, is cost-prohibitive. In this paper, we propose WILD, a supervised learning model to predict dynamic delay of functional units (FUs) based on the input workload during execution. We measure the dynamic delay using switching activity generated through gate-level simulation of a post place-and-route design in TSMC 45nm process. We then look for ‘features’ in the input data that influence dynamic path sensitization. Using these features we apply a logistic regression (LR) method to construct a predictive model trained and tested using three datasets: random, Sobel filter and Gaussian filter. We classify dynamic delay into five distinct classes. For a given test input, WILD predicts the class of output dynamic delay. On average across several FUs, 98.0% of WILD predictions are consistent with gate-level simulation. Using WILD-directed dynamic frequency scaling can improve instruction-level performance by 13%–44% compared to the state-of-the-art instruction-level timing model." @default.
- W2552045999 created "2016-11-30" @default.
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- W2552045999 date "2016-10-01" @default.
- W2552045999 modified "2023-09-26" @default.
- W2552045999 title "WILD: A workload-based learning model to predict dynamic delay of functional units" @default.
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- W2552045999 doi "https://doi.org/10.1109/iccd.2016.7753279" @default.
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